/ Embedded · 2023

Four-Function Calculator in Verilog

FSM + datapath implementing add/sub/mul/div with Booth’s algorithm, overflow detection, ModelSim verification.

Four-Function Calculator in Verilog

Overview

A hardware calculator implemented in Verilog HDL featuring a finite state machine controller and arithmetic datapath. Supports addition, subtraction, multiplication (using Booth's algorithm), and division. Includes overflow detection and was verified using ModelSim simulation.

Key Features

  • Four arithmetic operations: +, -, ×, ÷
  • Booth's algorithm for efficient multiplication
  • Overflow and underflow detection
  • FSM-based control logic
  • Synthesizable design for FPGA deployment
  • Comprehensive testbench verification

Technical Challenges

Implementing Booth's algorithm in hardware with correct sign handling, minimizing logic depth for timing closure, and creating exhaustive test cases.

Outcome

Successfully synthesized design meets timing at 50MHz target frequency. All arithmetic operations verified correct across 10,000+ random test vectors.

Technologies

  • Verilog
  • FSM
  • Booth’s Algorithm
  • Simulation