Pipelined Assembly Datapath Simulator

Overview

A comprehensive CPU pipeline simulator that models a 5-stage RISC architecture with realistic hazard detection, data forwarding, and branch prediction. Executes assembly programs and provides detailed cycle-by-cycle analysis of pipeline behavior, stalls, and performance metrics.

Key Features

• 5-stage pipeline: Fetch, Decode, Execute, Memory, Writeback
• Data forwarding to minimize stalls
• Branch prediction with taken/not-taken heuristics
• Hazard detection and resolution
• Cycle-accurate simulation
• Performance metrics and statistics output

Technical Challenges

Correctly implementing data forwarding paths, handling all edge cases for hazards, and ensuring the simulator matched expected behavior for complex instruction sequences.

Outcome

Created a teaching tool that helps students visualize pipeline operations. Achieved 85% accuracy in branch prediction on benchmark programs.

Technologies

• C
• Assembly
• Branch Prediction